CVE-2026-50185

RustCrypto Cmov/CmovEq on aarch64 can produce wrong results if high-bits of registers are set

LOW
3.3
CVSS Score
Published: July 17, 2026 at 06:35 PM UTC
Updated: October 24, 2026 at 08:10 PM UTC
1 product affected across 1 vendorCmov

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Severity
LOW3.3
Exploit prediction
EPSS 0.2%
SSVC
PoC

Description

RustCrypto CMOV provides conditional move CPU intrinsics which are guaranteed on major platforms to execute in constant-time and not be rewritten as branches by the compiler. From 0.1.1 until 0.5.4, the aarch64 implementations of Cmov and CmovEq in cmov/src/backends/aarch64.rs assume high bits are zero-extended when loading values smaller than a register, so set high bits such as [8..] in a Cmov selector or [16..] of self or other in the u16 and i16 CmovEq implementations can cause left.cmovz(&right, condition) to produce incorrect output. This issue is fixed in version 0.5.4.

Affected

Our own answer: ranges merged, affected separated from platform-only, with confidence and review flags.

0.1.1 ≤ v < 0.5.4
Affected range stops below 0.5.4, so it looks safe — our inference, not a vendor statement

Remediation

No guide yet

No remediation guidance has been written for this CVE yet. What the record does show:

References (3)

SSVC — Action Prioritization

SSVCPoCNot automatablePartial impact

SSVC signals action urgency (what to patch first), separate from CVSS which measures severity.

CVSS

Attack Vector
LOCAL
Complexity
LOW
Privileges
LOW
User Interaction
NONE
Scope
UNCHANGED
Confidentiality
NONE
Integrity
LOW
Availability
NONE
Vector?

Quick Info

StatusANALYZED
CWE
CWE-758

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