CVE-2026-23554
Use after free of paging structures in EPT
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Description
The Intel EPT paging code uses an optimization to defer flushing of any cached EPT state until the p2m lock is dropped, so that multiple modifications done under the same locked region only issue a single flush. Freeing of paging structures however is not deferred until the flushing is done, and can result in freed pages transiently being present in cached state. Such stale entries can point to memory ranges not owned by the guest, thus allowing access to unintended memory regions.
Remediation
No guide yetNo remediation guidance has been written for this CVE yet. What the record does show:
References (3)
SSVC — Action Prioritization
SSVC signals action urgency (what to patch first), separate from CVSS which measures severity.
CVSS
- Attack Vector
- LOCAL
- Complexity
- HIGH
- Privileges
- LOW
- User Interaction
- NONE
- Scope
- CHANGED
- Confidentiality
- HIGH
- Integrity
- HIGH
- Availability
- HIGH
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