CVE-2025-14857

Semtech LR11xx Memory Write Access Control Bypass

MEDIUM
5.4
CVSS Score
Published: April 7, 2026 at 07:56 PM UTC
Updated: July 24, 2026 at 11:20 PM UTC
3 products affected across 1 vendorLR1120LR1110LR1121

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Severity
MEDIUM5.4
Exploit prediction
EPSS 0.2%
SSVC
No known exploit

Description

An improper access control vulnerability exists in Semtech LoRa LR11xxx transceivers running early versions of firmware where the memory write command accessible via the physical SPI interface fails to enforce write protection on the program call stack. An attacker with physical access to the SPI interface can overwrite stack memory to hijack program control flow and achieve limited arbitrary code execution. However, the impact is limited to the active attack session: the device's secure boot mechanism prevents persistent firmware modification, the crypto engine isolates cryptographic keys from direct firmware access, and all modifications are lost upon device reboot or loss of physical access.

Affected

Our own answer: ranges merged, affected separated from platform-only, with confidence and review flags.

v < TRX FW 0x0402
Affected range stops below TRX FW 0x0402, so it looks safe — our inference, not a vendor statement
v < TRX FW 0x0202
Affected range stops below TRX FW 0x0202, so it looks safe — our inference, not a vendor statement
v < TRX FW 0x0104
Affected range stops below TRX FW 0x0104, so it looks safe — our inference, not a vendor statement

Remediation

No guide yet

No remediation guidance has been written for this CVE yet, and no fixed version or vendor advisory is recorded against it.

SSVC — Action Prioritization

SSVCNo known exploitNot automatableTotal impact

SSVC signals action urgency (what to patch first), separate from CVSS which measures severity.

CVSS

5.4MEDIUMSWI
Vector?

Quick Info

StatusAWAITING ANALYSIS
CWE
CWE-123

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