CVE-2023-31315

HIGH
7.5
CVSS Score
Published: August 9, 2024 at 05:08 PM UTC
Updated: June 17, 2026 at 05:56 AM UTC
36 products affected across 1 vendorRyzen 5000 SeriesEpyc Embedded 7003Ryzen Embedded R2000

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Severity
HIGH7.5
Exploit prediction
EPSS 0.6%
SSVC
No known exploit

Description

Improper validation in a model specific register (MSR) could allow a malicious program with ring0 access to modify SMM configuration while SMI lock is enabled, potentially leading to arbitrary code execution.

Affected

Our own answer: ranges merged, affected separated from platform-only, with confidence and review flags.

All versions
Vendor states this is fixed in EmbGenoaPI 1.0.0.7 (unaffected)
Vendor states this is fixed in emgenoa.pi.1.0.0.7 (unaffected)
All versions
Vendor states this is fixed in CezannePI-FP6 1.0.1.1 (unaffected)
Vendor states this is fixed in ComboAM4v2PI 1.2.0.cb (unaffected)
Vendor states this is fixed in cezannepi-fp6.1.0.1.1 (unaffected)
Vendor states this is fixed in comboam4v2pi.1.2.0.cb (unaffected)
All versions
Vendor states this is fixed in PhoenixPI-FP8-FP7 1.1.0.3 (unaffected)
Vendor states this is fixed in phoenixpi-fp8-fp7.1.1.0.3 (unaffected)

Remediation

No guide yet

No remediation guidance has been written for this CVE yet. What the record does show:

SSVC — Action Prioritization

SSVCNo known exploitNot automatableTotal impact

SSVC signals action urgency (what to patch first), separate from CVSS which measures severity.

CVSS

7.5HIGHAMD
Attack Vector
LOCAL
Complexity
HIGH
Privileges
HIGH
User Interaction
NONE
Scope
CHANGED
Confidentiality
HIGH
Integrity
HIGH
Availability
HIGH
Vector?

Quick Info

StatusDEFERRED
CWE
CWE-94

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